Traditional methods for specifying the timing constraints on an integrated circuit design fall into two categories: system level constraints entered by the user, and detailed path constraints generated automatically from the system level constraints. System level constraints are very compact and provide full coverage of the timing constraints on the entire design, but they require complicated timing analysis techniques to interpret accurately. Detailed path constraints are straightforward to interpret, and have therefore been used extensively in timing-driven placement and routing tools. However, the number of detailed path constraints required to provide reasonable coverage makes this approach unsuitable for very large designs. To address this problem, this invention defines a new formulation of timing constraints, which provides a compact representation with no loss of the information in system level constraints, yet is simple and efficient to interpret. Mechanisms for automatically generating these stage-based constraints are described, along with the use of the constraints for timing-driven placement, timing-driven routing, and incremental logic optimization.
As circuit density increases, deep-submicron effects on the ratio between interconnect delay and gate delays become increasingly important. These effects make it necessary to perform timing-driven placement, physically-based incremental logic optimization, and timing-driven routing.
Although existing techniques for passing timing constraints to placement and routing are well-established, we expect that in the near future these techniques will reach their limits in performance and capacity. As designs of more than a million gates become common-place, the traditional approach based on detailed path constraints will run into problems with the amount of time required to generate the constraints, the file size needed to pass them from tool to tool, and the memory usage and CPU time required to interpret them.
Worse, each of the existing techniques for generating detailed path constraints suffers from a lack of coverage. Some paths in the design go unconstrained, often because the number of path constraints is restricted to reduce their size, but also because the mechanisms for selecting the paths do not ensure that every path in the design is covered. One popular path selection technique, used in the Synopsys Design Compiler "cover_design" method of generating detailed path constraints, still suffers from a coverage problem for paths through reconvergent logic.
Because of this lack of coverage, detailed path constraints are not suitable for driving incremental logic optimization.